SIMULATOR=verilator
SIMU_PARAM=-I$(SIMU_INCDIR) #-I$(UVM_INCDIR)
SYNTHESIZER=qflow synthesize
HIERARCHY_FILE=$(REPORT_DIR)/hierarchy.rpt


RTL_DIR = ./RTL
TB_DIR=./SIMRTL
ASIC_PDK=osu018
OBJ_DIR=./temp
REPORT_DIR=./temp
INCLUDE_DIR=./RTL
SIMU_INCDIR=./SIMRTL
#UVM_INCDIR=./sim/uvm_library/src
TOP_MODULE=ysyx_210152
TB_MODULE=Vostok564_tb
SHOW_WAVEFORM=TRUE
BINARY_CASE=./TestBin